Advances in miniaturization of integrated circuits have led to smaller areas available for devices such as transistors and capacitors. For example, in semiconductor manufacture of a memory array for a dynamic random access memory (DRAM), each memory cell comprises a capacitor and a transistor. In a conventional DRAM, pairs of memory cells are located within regions ("memory cell areas") defined by intersecting row lines ("word lines") and column lines ("bit lines" or "digit lines"). Accordingly, to increase memory cell density of the memory array, row lines and column lines are positioned with minimal spacing ("pitch"). Using minimal pitch in turn constrains memory cell area.
In conflict with reducing memory cell area is maintaining a sufficient amount of memory cell charge storage capacitance. Each DRAM memory comprises a capacitor for storing charge. A capacitor is two conductors separated by a dielectric, and its capacitance, C, is mathematically determinable as: EQU C=(.epsilon..sub.r.epsilon..sub.o A)/d,
where .epsilon..sub.o is a physical constant; dielectric constant, .epsilon..sub.r, is a material dependant property; distance, d, is distance between conductors; and area, A, is common surface area of the two conductors.
Thus, to increase capacitance, C, by increasing area, A, the DRAM industry has shifted from planar capacitor structures (e.g., "parallel plate capacitors") to vertical capacitor structures (e.g., "container capacitors"). As suggested by its name, one version of a "container capacitor" may be envisioned as including cup-shape electrodes, one stacked within the other, separated by a dielectric layer or layers. Accordingly, a container capacitor structure provides more common surface area, A, within a memory cell area than its planar counterpart, and thus, container capacitors do not have to occupy as much memory cell area as their planar counterparts in order to provide an equivalent capacitance.
To increase a container capacitor's capacitance, others have suggested etching to expose exterior surface 9 of capacitor bottom electrode 20 all around each in-process container capacitor 8A, as illustratively shown in the top plan view of FIG. 1 and in the cross-sectional view of FIG. 2. This is in contrast to the conventional approach of only using interior surface 2, as illustratively shown in the cross-sectional view of FIG. 3.
With respect to FIG. 2, capacitor dielectric layer 23A and capacitor top electrode layer 24A are deposited on interior surface 2 and exterior surface 9 of capacitor bottom electrode 20. With respect to FIG. 3, capacitor dielectric layer 23B and capacitor top electrode layer 24B are deposited on interior surface 2 of capacitor bottom electrode 20. Accordingly, surface area, A, of container capacitor 8A of substrate assembly 10A will be greater than that of container capacitor 8B of substrate assembly 10B. By substrate assembly as used herein, it is meant a substrate having one or more layers formed thereon or therein. Moreover, in the current application, the term "substrate" or "semiconductor substrate" will be understood to mean any construction comprising semiconductor material, including but not limited to bulk semiconductive materials such as a semiconductor wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). Further, the term "substrate" also refers to any supporting structure including, but not limited to, the semiconductive substrates described above.
Container capacitor 8A poses problems for high-density memory array architectures. By high-density memory array architecture, it is meant a memory array with a bit line-to-bit line pitch equal to or less than 0.5 microns. Combined thickness of capacitor dielectric layer 23A and top capacitor electrode layer 24A is approximately 50 nm to 150 nm, and space 7 between capacitor bottom electrodes 20 exterior surface 9 and the contact site 5, indicated by dashed-lines, is approximately 200 nm or less. The contact site 5 designates a contact's current or eventual location. Forming capacitor dielectric layer 23A and top capacitor electrode layer 24A all around exterior surface 9 of capacitor bottom electrodes 20 encroaches upon nearby contact sites 5. While not wishing to be bound by theory, it is believed that this causes an increase in shorts between container capacitor 8A and contacts. This shorting may be due to diffusion and/or stress migration of material from capacitor top electrode layer 24A to one or more contacts. Moreover, such shorting may be due to residue left from a contact etch, as is explained below with respect to substrate assembly 10A.
With respect to substrate assembly 10A of FIG. 2, dielectric layer 60A is deposited on capacitor top electrode layer 24A, and then etch mask 61 is deposited and patterned for etching a contact via at the contact site 5. However, to provide the contact via, a portion of capacitor top electrode layer 24A and a portion of dielectric layer 23A at the bottom of the contact via must be cleared. Clearing materials at the bottom of a contact via is more problematic than clearing them at the top where they are more accessible. For example, a photo processes may not be tolerant enough to clear material from the bottom of the via given the via's diameter and depth.
In substrate assembly 10B of FIG. 3, dielectric layer 60B is deposited before deposition of capacitor top electrode layer 24B and dielectric layer 23B. Accordingly, those portions of capacitor top electrode layer 24B and dielectric layer 23B to be cleared for forming a contact via at the contact site 5 are more accessible than their counterparts in substrate assembly 10A.
Thus, there is a need in the art of container capacitors to provide a structure and process therefor which increases capacitance with less likelihood of the above-mentioned problems of shorts. Such structures and processes should also be more able to accommodate process limitations such as photo tolerance.